Datasheet

When CPHA = 0, the slave begins to drive its MISO output with the first data bit value
(MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge
causes both the master and the slave to sample the data bit values on their MISO and
MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit
position which shifts in the bit value that was just sampled and shifts the second data bit
value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively. When CPHA = 0, the slave's SS input must go to its inactive high
level between transfers.
16.4.5 SPI Baud Rate Generation
As shown in the following figure, the clock source for the SPI baud rate generator is the
bus clock. The three prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1,
2, 3, 4, 5, 6, 7, or 8. The three rate select bits (SPR3:SPR2:SPR1:SPR0) divide the output
of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, 256, or 512 to get the internal SPI master
mode bit-rate clock.
The baud rate generator is activated only when the SPI is in the master mode and a serial
transfer is taking place. In the other cases, the divider is disabled to decrease I
DD
current.
The baud rate divisor equation is as follows (except those reserved combinations in the
SPI Baud Rate Divisor table).
BaudRateDivisor = (SPPR + 1) × 2
(SPR + 1)
The baud rate can be calculated with the following equation:
BaudRate = BusClock / BaudRateDivisor
MASTER
SPI
BIT RATE
BAUD RATE DIVIDER
PRESCALER
BUS
CLOCK
SPPR2:SPPR1:SPPR0
SPR3:SPR2:SPR1:SPR0
DIVIDE BY
1, 2, 3, 4, 5, 6, 7, or 8
DIVIDE BY
2, 4, 8, 16, 32, 64, 128,
256, or 512
Figure 16-17. SPI Baud Rate Generation
16.4.6 Special Features
The following section shows the module special features.
Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 443