Datasheet

Note
Care must be taken when expecting data from a master while
the slave is in a wait mode or a stop mode where the peripheral
bus clock is stopped but internal logic states are retained. Even
though the shift register continues to operate, the rest of the SPI
is shut down (that is, an SPRF interrupt is not generated until an
exit from stop or wait mode). Also, the data from the shift
register is not copied into the SPIx_D registers until after the
slave SPI has exited wait or stop mode. An SPRF flag and
SPIx_D copy is only generated if wait mode is entered or exited
during a transmission. If the slave enters wait mode in idle
mode and exits wait mode in idle mode, neither an SPRF nor a
SPIx_D copy occurs.
16.4.8.3 SPI in Stop Mode
Operation in a stop mode where the peripheral bus clock is stopped but internal logic
states are retained depends on the SPI system. The stop mode does not depend on the
SPISWAI bit. Upon entry to this type of stop mode, the SPI module clock is disabled
(held high or low).
• If the SPI is in master mode and exchanging data when the CPU enters the stop
mode, the transmission is frozen until the CPU exits stop mode. After the exit from
stop mode, data to and from the external SPI is exchanged correctly.
• In slave mode, the SPI remains synchronized with the master.
The SPI is completely disabled in a stop mode where the peripheral bus clock is stopped
and internal logic states are not retained. After an exit from this type of stop mode, all
registers are reset to their default values, and the SPI module must be re-initialized.
16.4.9 Reset
The reset values of registers and signals are described in Register Definition, which
details the registers and their bitfields.
• If a data transmission occurs in slave mode after a reset without a write to SPIx_D,
the transmission consists of "garbage" or the data last received from the master
before the reset.
• Reading from SPIx_D after reset always returns zeros.
Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 447