Datasheet

• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
17.1.2 Modes of Operation
The SPI functions in three modes, run, wait, and stop.
• Run Mode
This is the basic mode of operation.
• Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the
SPISWAI bit located in the SPIx_C2 register. In wait mode, if the SPISWAI bit is
clear, the SPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into
a power conservative state, with the SPI clock generation turned off. If the SPI is
configured as a master, any transmission in progress stops, but is resumed after CPU
enters run mode. If the SPI is configured as a slave, reception and transmission of a
byte continues, so that the slave stays synchronized to the master.
• Stop Mode
To reduce power consumption, the SPI is inactive in stop modes where the peripheral
bus clock is stopped but internal logic states are retained. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after the CPU enters run
mode. If the SPI is configured as a slave, reception and transmission of a data
continues, so that the slave stays synchronized to the master.
Introduction
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
454 Freescale Semiconductor, Inc.