Datasheet

17.1.3.2 SPI Module Block Diagram
The following is a block diagram of the SPI module. The central element of the SPI is the
SPI shift register. Data is written to the double-buffered transmitter (write to
SPIx_DH:SPIx_DL) and gets transferred to the SPI shift register at the start of a data
transfer. After shifting in 8 bits or 16 bits (as determined by the SPIMODE bit) of data,
the data is transferred into the double-buffered receiver where it can be read from
SPIx_DH:SPIx_DL. Pin multiplexing logic controls connections between MCU pins and
the SPI module.
When the FIFO feature is supported: Additionally there is an 8-byte receive FIFO and an
8-byte transmit FIFO that (once enabled) provide features to allow fewer CPU interrupts
to occur when transmitting/receiving high volume/high speed data. When FIFO mode is
enabled, the SPI can still function in either 8-bit or 16-bit mode (as per SPIMODE bit)
and three additional flags help monitor the FIFO status. Two of these flags can provide
CPU interrupts.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the
shifter output is routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the
SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI
pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins
together, and all MOSI pins together. Peripheral devices often use slightly different
names for these pins.
Introduction
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
456 Freescale Semiconductor, Inc.