Datasheet

ENABLE
SPI SYSTEM
SHIFT
OUT
SHIFT
DIRECTION
SHIFT
Tx BUFFER (WRITE DH:DL)
SPI SHIFT REGISTER
Rx BUFFER (READ DH:DL)
PIN CONTROL
MASTER CLOCK
SLAVE CLOCK
BUS RATE
CLOCK
SPI BR
CLOCK GENERATOR
MASTER/SLAVE
MODE SELECT
CLOCK
LOGIC
MODE FAULT
DETECTION
16-BIT COMPARATOR
16-BIT LATCH
MASTER/
SLAVE
SPSCK
SS
S
M
S
M
S
M
MOSI
(MOMI)
MISO
(SISO)
SPI
INTERRUPT
REQUEST
SPE
LSBFE
MSTR
SPMF
SPMIE
SPTIE
SPIE
MODF
SPRF
SPTEF
MODFEN
SSOE
SPC0
BIDIROE
IN
FIFOMODE
Rx FIFO (64 bits deep)
Tx BUFFER
EMPTY
Rx BUFFER
FULL
SHIFT
CLOCK
Tx FIFO (64 bits deep)
8 OR 16
BIT MODE
SPIMODE
RNFULLF
RNFULLIEN
TNEAREF
TNEARIEN
MH:ML
Figure 17-2. SPI Module Block Diagram with FIFO
17.2 External Signal Description
The SPI optionally shares four port pins. The function of these pins depends on the
settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to
other functions that are not controlled by the SPI (based on chip configuration).
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 457