Datasheet

SPI1_C1 field descriptions (continued)
Field Description
0 Interrupts from SPRF and MODF are inhibited—use polling (when FIFOMODE is not present or is 0)
or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or
Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
6
SPE
SPI system enable
This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is
cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
0 SPI system inactive
1 SPI system enabled
5
SPTIE
SPI transmit interrupt enable
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This is the interrupt
enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer is
empty (SPTEF is set).
When the FIFO is supported and enabled (FIFOMODE is 1): This is the interrupt enable bit for SPI
transmit FIFO empty (SPTEF). An interrupt occurs when the SPI transmit FIFO is empty (SPTEF is set).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
4
MSTR
Master/slave mode select
This bit selects master or slave mode operation.
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
CPOL
Clock polarity
This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI
modules must have identical CPOL values.
This bit effectively places an inverter in series with the clock signal either from a master SPI device or to a
slave SPI device. Refer to the description of “SPI Clock Formats” for details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
2
CPHA
Clock phase
This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer
to the description of “SPI Clock Formats” for details.
0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer
1 First edge on SPSCK occurs at the start of the first cycle of a data transfer
1
SSOE
Slave select output enable
This bit is used in combination with the mode fault enable (MODFEN) bit in the C2 register and the master/
slave (MSTR) control bit to determine the function of the SS pin.
Table continues on the next page...
Memory Map and Register Descriptions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
460 Freescale Semiconductor, Inc.