Datasheet

SPI1_S field descriptions (continued)
Field Description
When FIFOMODE is 1: This bit indicates the status of the read FIFO when FIFOMODE is enabled. The
SPRF is set when the read FIFO has received 64 bits (4 words or 8 bytes) of data from the shifter and
there have been no CPU reads of the SPI data (DH:DL) register. SPRF is cleared by reading the SPI data
register, which empties the FIFO assuming another SPI message is not received.
0 No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is
not full (when FIFOMODE is 1)
1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full
(when FIFOMODE is 1)
6
SPMF
SPI match flag
SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the MH:ML
registers. To clear the flag, read SPMF when it is set and then write a 1 to it.
0 Value in the receive data buffer does not match the value in the MH:ML registers
1 Value in the receive data buffer matches the value in the MH:ML registers
5
SPTEF
SPI transmit buffer empty flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty
flag (when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This bit is set when
the transmit data buffer is empty. SPTEF is cleared by reading the S register with SPTEF set and then
writing a data value to the transmit buffer at DH:DL. The S register must be read with SPTEF set to 1
before writing data to the DH:DL register; otherwise, the DH:DL write is ignored. SPTEF is automatically
set when all data from the transmit buffer transfers into the transmit shift register. For an idle SPI, data
written to DH:DL is transferred to the shifter almost immediately so that SPTEF is set within two bus
cycles, allowing a second set of data to be queued into the transmit buffer. After completion of the transfer
of the data in the shift register, the queued data from the transmit buffer automatically moves to the shifter,
and SPTEF is set to indicate that room exists for new data in the transmit buffer. If no new data is waiting
in the transmit buffer, SPTEF simply remains set and no data moves from the buffer to the shifter.
When the FIFO is supported and enabled (FIFOMODE is 1): This bit provides the status of the FIFO rather
than of an 8-bit or a 16-bit buffer. This bit is set when the transmit FIFO is empty. SPTEF is cleared by
writing a data value to the transmit FIFO at DH:DL. SPTEF is automatically set when all data from the
transmit FIFO transfers into the transmit shift register. For an idle SPI, data written to the DH:DL register is
transferred to the shifter almost immediately, so that SPTEF is set within two bus cycles. A second write of
data to the DH:DL register clears this SPTEF flag. After completion of the transfer of the data in the shift
register, the queued data from the transmit FIFO automatically moves to the shifter, and SPTEF will be set
only when all data written to the transmit FIFO has been transfered to the shifter. If no new data is waiting
in the transmit FIFO, SPTEF simply remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when
FIFOMODE is 1)
1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when
FIFOMODE is 1)
4
MODF
Master mode fault flag
MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some
other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when
MSTR is 1, MODFEN is 1, and SSOE is 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1 and then writing to the SPI control register 1 (C1).
0 No mode fault error
1 Mode fault error detected
Table continues on the next page...
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 465