Datasheet

17.3.5 SPI data register high (SPIx_DH)
Refer to the description of the DL register.
Address: 30A0h base + 4h offset = 30A4h
Bit 7 6 5 4 3 2 1 0
Read
Bits[15:8]
Write
Reset
0 0 0 0 0 0 0 0
SPI1_DH field descriptions
Field Description
7–0
Bits[15:8]
Data (high byte)
17.3.6 SPI data register low (SPIx_DL)
This register, together with the DH register, is both the input and output register for SPI
data. A write to the registers writes to the transmit data buffer, allowing data to be queued
and transmitted.
When the SPI is configured as a master, data queued in the transmit data buffer is
transmitted immediately after the previous transmission has completed.
The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept
new data. The S register must be read when SPTEF is set before writing to the SPI data
registers; otherwise, the write is ignored.
Data may be read from the SPI data registers any time after SPRF is set and before
another transfer is finished. Failure to read the data out of the receive data buffer before a
new transfer ends causes a receive overrun condition, and the data from the new transfer
is lost. The new data is lost because the receive buffer still held the previous character
and was not ready to accept the new data. There is no indication for a receive overrun
condition, so the application system designer must ensure that previous data has been
read from the receive buffer before a new transfer is initiated.
In 8-bit mode, only the DL register is available. Reads of the DH register return all zeros.
Writes to the DH register are ignored.
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 467