Datasheet

In 16-bit mode, reading either byte (the DH or DL register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the DH or DL register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
Address: 30A0h base + 5h offset = 30A5h
Bit 7 6 5 4 3 2 1 0
Read
Bits[7:0]
Write
Reset
0 0 0 0 0 0 0 0
SPI1_DL field descriptions
Field Description
7–0
Bits[7:0]
Data (low byte)
17.3.7 SPI match register high (SPIx_MH)
Refer to the description of the ML register.
Address: 30A0h base + 6h offset = 30A6h
Bit 7 6 5 4 3 2 1 0
Read
Bits[15:8]
Write
Reset
0 0 0 0 0 0 0 0
SPI1_MH field descriptions
Field Description
7–0
Bits[15:8]
Hardware compare value (high byte)
17.3.8 SPI match register low (SPIx_ML)
This register, together with the MH register, contains the hardware compare value. When
the value received in the SPI receive data buffer equals this hardware compare value, the
SPI match flag (SPMF) sets.
In 8-bit mode, only the ML register is available. Reads of the MH register return all
zeros. Writes to the MH register are ignored.
Memory Map and Register Descriptions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
468 Freescale Semiconductor, Inc.