Datasheet

In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the MH or ML register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent value into the SPI match registers.
Address: 30A0h base + 7h offset = 30A7h
Bit 7 6 5 4 3 2 1 0
Read
Bits[7:0]
Write
Reset
0 0 0 0 0 0 0 0
SPI1_ML field descriptions
Field Description
7–0
Bits[7:0]
Hardware compare value (low byte)
17.3.9 SPI control register 3 (SPIx_C3)
This register introduces a 64-bit FIFO function on both transmit and receive buffers. It
applies only for an instance of the SPI module that supports the FIFO feature.
FIFO mode is enabled by setting the FIFOMODE bit to 1. A write to this register occurs
only when it sets the FIFOMODE bit to 1.
Using this FIFO feature allows the SPI to provide high speed transfers of large amounts
of data without consuming large amounts of the CPU bandwidth.
Enabling this FIFO function affects the behavior of some of the read/write buffer flags in
the S register as follows:
• The SPRF of the S register is 1 when the receive FIFO is filled. As a result:
• If the SPIE bit in the C1 register is 1, SPRF interrupts the CPU.
• The SPTEF of the S register is 1 when the transmit FIFO is empty. As a result:
• If the SPTIE bit in the C1 register is 1, SPTEF interrupts the CPU.
Two interrupt enable bits, TNEARIEN and RNFULLIEN, provide CPU interrupts based
on the "watermark" feature of the TNEARF and RNFULLF flags of the S register.
Address: 30A0h base + 8h offset = 30A8h
Bit 7 6 5 4 3 2 1 0
Read 0 TNEAREF_
MARK
RNFULLF_
MARK
INTCLR TNEARIEN RNFULLIEN FIFOMODE
Write
Reset
0 0 0 0 0 0 0 0
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 469