Datasheet

Optional Manual Reset
BKGD/MS
V
DD
V
SS
PTA5/IRQ/TCLK0/RESET
Figure 2-8. Typical debug circuit
2.2.6 Port A input/output (I/O) pins (PTA–PTA0)
PTA–PTA0 except PTA4 are general-purpose, bidirectional I/O port pins. These port
pins also have selectable pullup devices when configured for input mode except PTA4,
the pullup devices are selectable on an individual port bit basis. The pulling devices are
disengaged when configured for output mode except when PTA2 and PTA3 are used as
SDA and SCL function.
PTA3 and PTA2 provide true open drain when operated as output.
2.2.7 Port B input/output (I/O) pins (PTB7–PTB0)
PTB7–PTB0 are general-purpose, bidirectional I/O port pins. These port pins also have
selectable pullup devices when configured for input mode, the pullup devices are
selectable on an individual port bit basis. The pulling devices are disengaged when
configured for output mode.
2.2.8 Port C input/output (I/O) pins (PTC–PTC0)
PTC–PTC0 are general-purpose, bidirectional I/O port pins. These port pins also have
selectable pullup devices when configured for input mode, the pullup devices are
selectable on an individual port bit basis. The pulling devices are disengaged when
configured for output mode.
2.2.9 True open drain pins (PTA3–PTA2)
PTA3 and PTA2 operate in true open-drain mode.
Chapter 2 Pins and connections
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 47