Datasheet

SPI1_C3 field descriptions
Field Description
7–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
TNEAREF_
MARK
Transmit FIFO nearly empty watermark
This bit selects the mark after which the TNEAREF flag is asserted.
0 TNEAREF is set when the transmit FIFO has 16 bits or less
1 TNEAREF is set when the transmit FIFO has 32 bits or less
4
RNFULLF_
MARK
Receive FIFO nearly full watermark
This bit selects the mark after which the RNFULLF flag is asserted.
0 RNFULLF is set when the receive FIFO has 48 bits or more
1 RNFULLF is set when the receive FIFO has 32 bits or more
3
INTCLR
Interrupt clearing mechanism select
This bit selects the mechanism by which the SPRF, SPTEF, TNEAREF, and RNFULLF interrupts are
cleared.
0 These interrupts are cleared when the corresponding flags are cleared depending on the state of the
FIFOs
1 These interrupts are cleared by writing the corresponding bits in the CI register
2
TNEARIEN
Transmit FIFO nearly empty interrupt enable
Writing 1 to this bit enables the SPI to interrupt the CPU when the TNEAREF flag is set. This bit is ignored
and has no function if the FIFOMODE bit is 0.
0 No interrupt upon TNEAREF being set
1 Enable interrupts upon TNEAREF being set
1
RNFULLIEN
Receive FIFO nearly full interrupt enable
Writing 1 to this bit enables the SPI to interrupt the CPU when the RNFULLF flag is set. This bit is ignored
and has no function if the FIFOMODE bit is 0.
0 No interrupt upon RNFULLF being set
1 Enable interrupts upon RNFULLF being set
0
FIFOMODE
FIFO mode enable
This bit enables the SPI to use a 64-bit FIFO (8 bytes or four 16-bit words) for both transmit and receive
buffers.
0 Buffer mode disabled
1 Data available in the receive data buffer
17.3.10 SPI clear interrupt register (SPIx_CI)
This register applies only for an instance of the SPI module that supports the FIFO
feature.
Memory Map and Register Descriptions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
470 Freescale Semiconductor, Inc.