Datasheet

The register has four bits dedicated to clearing the interrupts. Writing 1 to these bits
clears the corresponding interrupts if the INTCLR bit in the C3 register is 1. Reading
these bits always returns 0.
This register also has two read-only bits to indicate the transmit FIFO and receive FIFO
overrun conditions. When the receive FIFO is full and data is received, RXFOF is set.
Similarily, when the transmit FIFO is full and a write to the data register occurs, TXFOF
is set. These flags are cleared when the CI register is read while the flags are set.
The register has two more read-only bits to indicate the error flags. These flags are set
when, due to some spurious reason, entries in the FIFO become greater than 8. At this
point, all the flags in the status register are reset, and entries in the FIFO are flushed with
the corresponding error flags set. These flags are cleared when the CI register is read
while the flags are set.
Address: 30A0h base + 9h offset = 30A9h
Bit 7 6 5 4 3 2 1 0
Read TXFERR RXFERR TXFOF RXFOF
0 0
0 0
Write
TNEAREFCI RNFULLFCI
SPTEFCI SPRFCI
Reset
0 0 0 0 0 0 0 0
SPI1_CI field descriptions
Field Description
7
TXFERR
Transmit FIFO error flag
This flag indicates that a transmit FIFO error occurred because entries in the FIFO exceed 8.
0 No transmit FIFO error occurred
1 A transmit FIFO error occurred
6
RXFERR
Receive FIFO error flag
This flag indicates that a receive FIFO error occurred because entries in the FIFO exceed 8.
0 No receive FIFO error occurred
1 A receive FIFO error occurred
5
TXFOF
Transmit FIFO overflow flag
This flag indicates that a transmit FIFO overflow condition has occurred.
0 Transmit FIFO overflow condition has not occurred
1 Transmit FIFO overflow condition occurred
4
RXFOF
Receive FIFO overflow flag
This flag indicates that a receive FIFO overflow condition has occurred.
0 Receive FIFO overflow condition has not occurred
1 Receive FIFO overflow condition occurred
3
TNEAREFCI
Transmit FIFO nearly empty flag clear interrupt
Table continues on the next page...
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 471