Datasheet

SPI1_CI field descriptions (continued)

Field Description

Writing 1 to this bit clears the TNEAREF interrupt provided that C3[3] is set.

RNFULLFCI

Receive FIFO nearly full flag clear interrupt

Writing 1 to this bit clears the RNFULLF interrupt provided that C3[3] is set.

SPTEFCI

Transmit FIFO empty flag clear interrupt

Writing 1 to this bit clears the SPTEF interrupt provided that C3[3] is set.

SPRFCI

Receive FIFO full flag clear interrupt

Writing 1 to this bit clears the SPRF interrupt provided that C3[3] is set.

17.4 Functional Description

This section provides the functional description of the module.

17.4.1 General

The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1.

While the SPE bit is set, the four associated SPI port pins are dedicated to the SPI

function as:

• Slave select (SS)

• Serial clock (SPSCK)

• Master out/slave in (MOSI)

• Master in/slave out (MISO)

An SPI transfer is initiated in the master SPI device by reading the SPI status register

(SPIx_S) when SPTEF = 1 and then writing data to the transmit data buffer (write to

SPIx_DH:SPIx_DL). When a transfer is complete, received data is moved into the

receive data buffer. The SPIx_DH:SPIx_DL registers act as the SPI receive data buffer

for reads and as the SPI transmit data buffer for writes.

The clock phase control bit (CPHA) and clock polarity control bit (CPOL) in the SPI

Control Register 1 (SPIx_C1) select one of four possible clock formats to be used by the

SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit

is used to accommodate two fundamentally different protocols by sampling data on odd

numbered SPSCK edges or on even numbered SPSCK edges.

Functional Description

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

472 Freescale Semiconductor, Inc.