Datasheet

delay, SPSCK is started within the master. The rest of the transfer operation

differs slightly, depending on the clock format specified by the SPI clock phase

bit, CPHA, in SPI Control Register 1 (see SPI Clock Formats).

Note

A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN,

SPC0, BIDIROE with SPC0 set, SPIMODE, FIFOMODE,

SPPR2-SPPR0 and SPR3-SPR0 in master mode abort a

transmission in progress and force the SPI into idle state. The

remote slave cannot detect this, therefore the master has to

ensure that the remote slave is set back to idle state.

17.4.3 Slave Mode

The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear.

• SPSCK

In slave mode, SPSCK is the SPI clock input from the master.

• MISO, MOSI pin

In slave mode, the function of the serial data output pin (MISO) and serial data input

pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register

• SS pin

The SS pin is the slave select input. Before a data transmission occurs, the SS pin of

the slave SPI must be low. SS must remain low until the transmission is complete. If

SS goes high, the SPI is forced into an idle state.

The SS input also controls the serial data output pin. If SS is high (not selected), the

serial data output pin is high impedance. If SS is low, the first bit in the SPI Data

(SS is high), then the SPSCK input is ignored and no internal shifting of the SPI shift

Although the SPI is capable of duplex operation, some SPI peripherals are capable of

only receiving SPI data in a slave mode. For these simpler devices, there is no serial

data out pin.

Functional Description

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

474 Freescale Semiconductor, Inc.