Datasheet

Note

When peripherals with duplex capability are used, take care not

to simultaneously enable two receivers whose serial outputs

drive the same system slave's serial data output line.

As long as no more than one slave device drives the system slave's serial data output line,

it is possible for several slaves to receive the same transmission from a master, although

the master would not receive return information from all of the receiving slaves.

If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SPSCK

input cause the data at the serial data input pin to be latched. Even numbered edges cause

the value previously latched from the serial data input pin to shift into the LSB or MSB

of the SPI shift register, depending on the LSBFE bit.

If the CPHA bit is set, even numbered edges on the SPSCK input cause the data at the

serial data input pin to be latched. Odd numbered edges cause the value previously

latched from the serial data input pin to shift into the LSB or MSB of the SPI shift

When CPHA is set, the first edge is used to get the first data bit onto the serial data output

pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI

data is driven out of the serial data output pin. After the eighth (SPIMODE = 0) or

sixteenth (SPIMODE = 1) shift, the transfer is considered complete and the received data

is transferred into the SPI Data register. To indicate transfer is complete, the SPRF flag in

the SPI Status Register is set.

Note

A change of the bits FIFOMODE,SPIMODE, BIDIROE with

SPC0 set, CPOL, CPHA, SSOE, LSBFE, MODFEN, and SPC0

in slave mode will corrupt a transmission in progress and must

be avoided.

17.4.4 SPI FIFO Mode

When the FIFO feature is supported: The SPI works in FIFO mode when the

C3[FIFOMODE] bit is set. When the module is in FIFO mode, the SPI RX buffer and

SPI TX buffer are replaced by an 8-byte-deep FIFO, as the following figures show.

Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

Freescale Semiconductor, Inc. 475