Datasheet

SPI Data Register
IPBus (ips_rdata[7:0])
Read Access
SPI_REG_BLOCK
FIFO Ctrlr
SPI_CORE_SHFR
FIFO depth = 8 bytes
Load
Control
RX- FIFO
shfr_rx_reg
spidh:l_rx_reg
Figure 17-23. SPIH:L read side structural overview in FIFO mode
IPBus (ips_rdata[7:0])
Read Access
SPI_CORE_SHFR
FIFO Ctrlr
FIFO depth = 8 bytes
Read
Control
TX- FIFO
shfr_tx_reg
SPI_REG_BLOCK
SPI Data Register
spidh:l_tx_reg
Figure 17-24. SPIH:L write side structural overview in FIFO mode
17.4.5 Data Transmission Length
The SPI can support data lengths of 8 or 16 bits. The length can be configured with the
SPIMODE bit in the SPIx_C2 register.
In 8-bit mode (SPIMODE = 0), the SPI Data Register is comprised of one byte:
SPIx_DL. The SPI Match Register is also comprised of only one byte: SPIx_ML. Reads
of SPIx_DH and SPIx_MH will return zero. Writes to SPIx_DH and SPIx_MH will be
ignored.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
476 Freescale Semiconductor, Inc.