Datasheet

17.4.10.3 SPI in Stop Mode
Operation in a stop mode where the peripheral bus clock is stopped but internal logic
states are retained depends on the SPI system. The stop mode does not depend on the
SPISWAI bit. Upon entry to this type of stop mode, the SPI module clock is disabled
(held high or low).
• If the SPI is in master mode and exchanging data when the CPU enters the stop
mode, the transmission is frozen until the CPU exits stop mode. After the exit from
stop mode, data to and from the external SPI is exchanged correctly.
• In slave mode, the SPI remains synchronized with the master.
The SPI is completely disabled in a stop mode where the peripheral bus clock is stopped
and internal logic states are not retained. After an exit from this type of stop mode, all
registers are reset to their default values, and the SPI module must be re-initialized.
17.4.11 Reset
The reset values of registers and signals are described in the Memory Map and Register
Descriptions content, which details the registers and their bitfields.
• If a data transmission occurs in slave mode after a reset without a write to
SPIx_DH:SPIx_DL, the transmission consists of "garbage" or the data last received
from the master before the reset.
• Reading from SPIx_DH:SPIx_DL after reset always returns zeros.
17.4.12 Interrupts
The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the
SPIx_C1 register is set). The following is a description of how the SPI makes a request
and how the MCU should acknowledge that request. The interrupt vector offset and
interrupt priority are chip dependent.
Four flag bits, three interrupt mask bits, and one interrupt vector are associated with the
SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI
receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable
mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF). The
SPI match interrupt enable mask bit (SPIMIE) enables interrupts from the SPI match flag
(SPMF). When one of the flag bits is set, and the associated interrupt mask bit is set, a
hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared,
software can poll the associated flag bits instead of using interrupts. The SPI interrupt
Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 485