Datasheet

1. Update control register 1 (SPIx_C1) to enable the SPI and to control interrupt

enables. This register also sets the SPI as master or slave, determines clock phase and

polarity, and configures the main SPI options.

2. Update control register 2 (SPIx_C2) to enable additional SPI functions such as the

SPI match interrupt feature, the master mode-fault function, and bidirectional mode

output as well as to control 8- or 16-bit mode selection and other optional features.

3. Update the baud rate register (SPIx_BR) to set the prescaler and bit rate divisor for

an SPI master.

4. Update the hardware match register (SPIx_MH:SPIx_ML) with the value to be

compared to the receive data register for triggering an interrupt if hardware match

interrupts are enabled.

5. In the master, read SPIx_S while SPTEF = 1, and then write to the transmit data

17.5.2 Pseudo-Code Example

In this example, the SPI module is set up for master mode with only hardware match

interrupts enabled. The SPI runs in 16-bit mode at a maximum baud rate of bus clock

divided by 2. Clock phase and polarity are set for an active-high SPI clock where the first

edge on SPSCK occurs at the start of the first cycle of a data transfer.

SPIx_C1=0x54(%01010100)

Bit 7 SPIE = 0 Disables receive and mode fault interrupts

Bit 6 SPE = 1 Enables the SPI system

Bit 5 SPTIE = 0 Disables SPI transmit interrupts

Bit 4 MSTR = 1 Sets the SPI module as a master SPI device

Bit 3 CPOL = 0 Configures SPI clock as active-high

Bit 2 CPHA = 1 First edge on SPSCK at start of first data transfer cycle

Bit 1 SSOE = 0 Determines SS pin function when mode fault enabled

Bit 0 LSBFE = 0 SPI serial data transfers start with most significant bit

SPIx_C2 = 0xC0(%11000000)

Bit 7 SPMIE = 1 SPI hardware match interrupt enabled

Bit 6 SPIMODE = 1 Configures SPI for 16-bit mode

Bit 5 = 0 Reserved

Bit 4 MODFEN = 0 Disables mode fault function

Bit 3 BIDIROE = 0 SPI data I/O pin acts as input

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Initialization/Application Information

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

488 Freescale Semiconductor, Inc.