Datasheet

18.3.3 I2C Control Register 1 (I2C_C1)
Address: 3070h base + 2h offset = 3072h
Bit 7 6 5 4 3 2 1 0
Read
IICEN IICIE MST TX TXAK
0
WUEN
0
Write RSTA
Reset
0 0 0 0 0 0 0 0
I2C_C1 field descriptions
Field Description
7
IICEN
I2C Enable
Enables I2C module operation.
0 Disabled
1 Enabled
6
IICIE
I2C Interrupt Enable
Enables I2C interrupt requests.
0 Disabled
1 Enabled
5
MST
Master Mode Select
When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master mode
is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operation
changes from master to slave.
0 Slave mode
1 Master mode
4
TX
Transmit Mode Select
Selects the direction of master and slave transfers. In master mode this bit must be set according to the
type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave
this bit must be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
3
TXAK
Transmit Acknowledge Enable
Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave
receivers. The value of the FACK bit affects NACK/ACK generation.
NOTE: SCL is held low until TXAK is written.
0 An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the
current receiving byte (if FACK is set).
1 No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or
the current receiving data byte (if FACK is set).
Table continues on the next page...
Memory map and register descriptions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
498 Freescale Semiconductor, Inc.