Datasheet

Table 2-1. Pin availability by package pin-count (continued)
Pin Number Lowest Priority <-- --> Highest
64-LQFP
64-QFP
48-LQFP 44-LQFP 32-LQFP Port Pin Alt 1 Alt 2 Alt 3 Alt 4
42 PTF1
43 PTF0
44 32 29 PTD4 KBI1P4
45 33 30 21 PTD3 KBI1P3 SS1
46 34 31 22 PTD2 KBI1P2 MISO1
47 35 32 23 PTA3
2
KBI0P3 TXD0 SCL
48 36 33 24 PTA2
2
KBI0P2 RXD0 SDA
49 37 34 25 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1
50 38 35 26 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0
51 39 36 27 PTC7 TxD1
52 40 37 28 PTC6 RxD1
53 41 PTE3 SS0
54 42 38 PTE2 MISO0
55 PTG3
56 PTG2
57 PTG1
58 PTG0
59 43 39 PTE1
1
MOSI0
60 44 40 PTE0
1
SPSCK0 TCLK1
61 45 41 29 PTC5 FTM1CH1
62 46 42 30 PTC4 FTM1CH0 RTCO
63 47 43 31 PTA5 IRQ TCLK0 RESET
64 48 44 32 PTA4 ACMPO BKGD MS
1. This is a high current drive pin when operated as output. Please see High current drive for more information.
2. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. The table above
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
Pin functions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
50 Freescale Semiconductor, Inc.