Datasheet

I2C_C2 field descriptions (continued)
Field Description
6
ADEXT
Address Extension
Controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
RMEN
Range Address Matching Enable
This bit controls slave address matching for addresses between the values of the A1 and RA registers.
When this bit is set, a slave address match occurs for any address greater than the value of the A1
register and less than or equal to the value of the RA register.
0 Range mode disabled. No address match occurs for an address within the range of values of the A1
and RA registers.
1 Range mode enabled. Address matching occurs when a slave receives an address within the range of
values of the A1 and RA registers.
2–0
AD[10:8]
Slave Address
Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only
while the ADEXT bit is set.
18.3.7 I2C Programmable Input Glitch Filter register (I2C_FLT)
Address: 3070h base + 6h offset = 3076h
Bit 7 6 5 4 3 2 1 0
Read
Reserved
0
FLT
Write
Reset
0 0 0 0 0 0 0 0
I2C_FLT field descriptions
Field Description
7
Reserved
This field is reserved.
Writing this bit has no effect.
6–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4–0
FLT
I2C Programmable Filter Factor
Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. For any glitch
whose size is less than or equal to this width setting, the filter does not allow the glitch to pass.
00h No filter/bypass
01-1Fh Filter glitches up to width of n bus clock cycles, where n=1-31d
Memory map and register descriptions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
502 Freescale Semiconductor, Inc.