Datasheet

18.3.12 I2C SCL Low Timeout Register Low (I2C_SLTL)
Address: 3070h base + Bh offset = 307Bh
Bit 7 6 5 4 3 2 1 0
Read
SSLT[7:0]
Write
Reset
0 0 0 0 0 0 0 0
I2C_SLTL field descriptions
Field Description
7–0
SSLT[7:0]
Least significant byte of SCL low timeout value that determines the timeout period of SCL low.
18.4 Functional description
This section provides a comprehensive functional description of the I2C module.
18.4.1 I2C protocol
The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data
transfers. All devices connected to it must have open drain or open collector outputs. A
logic AND function is exercised on both lines with external pull-up resistors. The value
of these resistors depends on the system.
Normally, a standard instance of communication is composed of four parts:
1. START signal
2. Slave address transmission
3. Data transfer
4. STOP signal
The STOP signal should not be confused with the CPU STOP instruction. The following
figure illustrates I2C bus system communication.
Functional description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
506 Freescale Semiconductor, Inc.