Datasheet

19.1.2 Block Diagram
This figure provides a block diagram of the ADC module.
AFDEP
AIEN
Analog Result
FIF
O
Fulfilled
Off-chip Source Channels
AD0 to AD15 from External
Pin Inputs or Reserved
Reserved
Reserved
Temperature Sensor
Internal Bandgap
Reserved
V
REFL
V
REFH
None (Module Disabled)
On-chip Source Channels
AHDWT
ALT CLK
BUS CLK
ADACK
ASYNC
CLOCK
GENERATOR
ADICLK ADIV
CLOCK
DIVIDER
ADCO STOP
ADTRG
MODE
ADLSMP ADLPC ACFGT
ACFE
CONTROL
SEQUENCER
COMPARE
LOGIC
ADCK
COCO
Interrupt to CPU
Input Channel
FIFO Fulfilled
AD0
AD1
AD2
AD14
AD15
AD16
AD21-AD20
AD22
AD23
AD29
AD30
AD31
AD32
Compare Value
2
ANALOG MUX
CLK MUX
AD CHANNEL FIFO
AD RESULT FIFO
12-bit AD result
12-bit AD result
12-bit AD result
12-bit AD result
12-bit AD result
12-bit AD result
12-bit AD result
12-bit AD result
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
SAR ADC
Figure 19-1. ADC Block Diagram
19.2 External Signal Description
The ADC module supports up to 24 separate analog inputs. It also requires four supply/
reference/ground connections.
External Signal Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
524 Freescale Semiconductor, Inc.