Datasheet

ADC_SC2 field descriptions (continued)
Field Description
0 Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO.
1 Indicates that ADC result FIFO is full and next conversion will override old data in case of no read
action.
1–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19.3.3 Status and Control Register 3 (ADC_SC3)
ADC_SC3 selects the mode of operation, clock source, clock divide, and configure for
low power or long sample time.
Address: 10h base + 2h offset = 12h
Bit 7 6 5 4 3 2 1 0
Read
ADLPC ADIV ADLSMP MODE ADICLK
Write
Reset
0 0 0 0 0 0 0 0
ADC_SC3 field descriptions
Field Description
7
ADLPC
Low-Power Configuration
ADLPC controls the speed and power configuration of the successive approximation converter. This
optimizes power consumption when higher sample rates are not required.
0 High speed configuration.
1 Low power configuration:The power is reduced at the expense of maximum clock speed.
6–5
ADIV
Clock Divide Select
ADIV selects the divide ratio used by the ADC to generate the internal clock ADCK.
00 Divide ration = 1, and clock rate = Input clock.
01 Divide ration = 2, and clock rate = Input clock ÷ 2.
10 Divide ration = 3, and clock rate = Input clock ÷ 4.
11 Divide ration = 4, and clock rate = Input clock ÷ 8.
4
ADLSMP
Long Sample Time Configuration
ADLSMP selects between long and short sample time. This adjusts the sample period to allow higher
impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs.
Longer sample times can also be used to lower overall power consumption when continuous conversions
are enabled if high conversion rates are not required.
0 Short sample time.
1 Long sample time.
3–2
MODE
Conversion Mode Selection
MODE bits are used to select between 12-, 10-, or 8-bit operation.
Table continues on the next page...
Chapter 19 Analog-to-digital converter (ADC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 529