Datasheet

3.2.4 Active BDM enabled in stop3 mode

Entry into the active background mode from run mode is enabled if the

BDC_SCR[ENBDM] bit is set. This register is described in the development support. If

BDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the system

clocks to the background debug logic remain active when the MCU enters stop mode, so

background debug communication is still possible. In addition, the voltage regulator does

not enter its low-power standby state but maintains full internal regulation.

Most background commands are not available in stop mode. The memory-access-with-

status commands do not allow memory access, but they report an error indicating that the

MCU is in either stop or wait mode. The BACKGROUND command can be used to

wake the MCU from stop and enter active background mode if the BDC_SCR[ENBDM]

bit is set. After entering background debug mode, all background commands are

available.

3.2.5 LVD enabled in stop mode

The LVD system is capable of generating either an interrupt or a reset when the supply

voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE

bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the

voltage regulator remains active during stop3 mode.

3.2.6 Power modes behaviors

Executing the WAIT or STOP command puts the MCU in a low power consumption

mode for standby situations. The system integration module (SIM) holds the CPU in a

non-clocked state. The operation of each of these modes is described in the following

subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code

behaviors.

Table 3-1. Low power mode behavior

Mode Run Wait Stop3

PMC Full regulation Full regulation Loose regulation

ICS On On Optional on

OSC On On Optional on

LPO On On On

CPU On Standby Standby

FLASH On On Standby

Table continues on the next page...

Chapter 3 Power management

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

Freescale Semiconductor, Inc. 53