Datasheet

ADC_SC4 field descriptions (continued)
Field Description
2–0
AFDEP
FIFO Depth enables the FIFO function and sets the depth of FIFO. When AFDEP is cleared, the FIFO is
disabled. When AFDEP is set to nonzero, the FIFO function is enabled and the depth is indicated by the
AFDEP bits. The ADCH in ADCSC1 and ADCRH:ADCRL must be accessed by FIFO mode when FIFO
function is enabled. ADC starts conversion when the analog channel FIFO is upon the level indicated by
AFDEP bits. The COCO bit is set when the set of conversions are completed and the result FIFO is upon
the level indicated by AFDEP bits.
000 FIFO is disabled.
001 2-level FIFO is enabled.
010 3-level FIFO is enabled..
011 4-level FIFO is enabled.
100 5-level FIFO is enabled.
101 6-level FIFO is enabled.
110 7-level FIFO is enabled.
111 8-level FIFO is enabled.
19.3.5 Conversion Result High Register (ADC_RH)
In 12-bit operation, ADC_RH contains the upper four bits of the result of a 12-bit
conversion.
ADC_RH is updated each time a conversion completes except when automatic compare
is enabled and the compare condition is not met. Reading ADC_RH prevents the ADC
from transferring subsequent conversion results into the result registers until ADC_RL is
read. If ADC_RL is not read until after the next conversion is completed, the intermediate
conversion result is lost. In 8-bit mode, there is no interlocking with ADC_RL.
When FIFO is enabled, the result FIFO is read via ADC_RH:ADC_RL. The ADC
conversion completes when the input channel FIFO is fulfilled at the depth indicated by
the AFDEP. The AD result FIFO can be read via ADCRH:ADCRL continuously by the
order set in analog input channel ADCH.
If the MODE bits are changed, any data in ADC_RH becomes invalid.
Address: 10h base + 4h offset = 14h
Bit 7 6 5 4 3 2 1 0
Read ADR
Write
Reset
0 0 0 0 0 0 0 0
Chapter 19 Analog-to-digital converter (ADC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 531