Datasheet

ADC_RH field descriptions
Field Description
7–0
ADR
Conversion Result[15:8]
19.3.6 Conversion Result Low Register (ADC_RL)
ADC_RL contains the lower eight bits of the result of a 12-bit conversion. This register is
updated each time a conversion completes except when automatic compare is enabled
and the compare condition is not met. In 12-bit mode, reading ADC_RH prevents the
ADC from transferring subsequent conversion results into the result registers until
ADC_RL is read. If ADC_RL is not read until the next conversion is completed, the
intermediate conversion results are lost. In 8-bit mode, there is no interlocking with
ADC_RH. If the MODE bits are changed, any data in ADC_RL becomes invalid.
When FIFO is enabled, the result FIFO is read via ADC_RH:ADC_RL. The ADC
conversion completes when the input channel FIFO is fulfilled at the depth indicated by
the AFDEP. The AD result FIFO can be read via ADC_RH:ADC_RL continuously by
the order set in analog input channel FIFO.
Address: 10h base + 5h offset = 15h
Bit 7 6 5 4 3 2 1 0
Read ADR
Write
Reset
0 0 0 0 0 0 0 0
ADC_RL field descriptions
Field Description
7–0
ADR
Conversion Result[7:0]
ADC Control Registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
532 Freescale Semiconductor, Inc.