Datasheet

The ADC module has the capability of automatically comparing the result of a
conversion with the contents of its compare registers. The compare function is enabled by
setting the ADC_SC2[ACFE] bit and operates with any of the conversion modes and
configurations.
19.4.1 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module. This
clock source is then divided by a configurable value to generate the input clock to the
converter (ADCK). The clock is selected from one of the following sources by means of
the ADC_SC3[ADICLK] bits.
• The bus clock, which is equal to the frequency at which software is executed. This is
the default selection following reset.
• The bus clock divided by two. For higher bus clock rates, this allows a maximum
divide by 16 of the bus clock.
• ALTCLK, that is, alternate clock which is OSCOUT
• The asynchronous clock (ADACK). This clock is generated from a clock source
within the ADC module. When selected as the clock source, this clock remains active
while the MCU is in wait or stop3 mode and allows conversions in these modes for
lower noise operation.
Whichever clock is selected, its frequency must fall within the specified frequency range
for ADCK. If the available clocks are too slow, the ADC do not perform according to
specifications. If the available clocks are too fast, the clock must be divided to the
appropriate frequency. This divider is specified by the ADC_SC3[ADIV] bits and can be
divide-by 1, 2, 4, or 8.
19.4.2 Input select and pin control
The pin control registers ( ADC_APCTL2 and ADC_APCTL1) disable the I/O port
control of the pins used as analog inputs. When a pin control register bit is set, the
following conditions are forced for the associated MCU pin:
• The output buffer is forced to its high impedance state.
Chapter 19 Analog-to-digital converter (ADC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 537