Datasheet

If continuous conversions are enabled, a new conversion is automatically initiated after
the completion of the current conversion. In software triggered operation, continuous
conversions begin after ADC_SC1 is written and continue until aborted. In hardware
triggered operation, continuous conversions begin after a hardware trigger event and
continue until aborted.
19.4.4.2 Completing conversions
A conversion is completed when the result of the conversion is transferred into the data
result registers, ADC_RH and ADC_RL. This is indicated by the setting of
ADC_SC1[COCO]. An interrupt is generated if ADC_SC1[AIEN] is high at the time that
ADC_SC1[COCO] is set.
A blocking mechanism prevents a new result from overwriting previous data in ADC_RH
and ADC_RL if the previous data is in the process of being read while in 12-bit or 10-bit
MODE (the ADC_RH register has been read but the ADC_RL register has not). When
blocking is active, the data transfer is blocked, ADC_SC1[COCO] is not set, and the new
result is lost. In the case of single conversions with the compare function enabled and the
compare condition false, blocking has no effect and ADC operation is terminated. In all
other cases of operation, when a data transfer is blocked, another conversion is initiated
regardless of the state of ADC_SC1[ADCO] whether single or continuous conversions
are enabled.
If single conversions are enabled, the blocking mechanism could result in several
discarded conversions and excess power consumption. To avoid this issue, the data
registers must not be read after initiating a single conversion until the conversion
completes.
In fifo mode, a blocking mechanism will keep current channel conversion and no channel
fifo and result fifo switching until a block mechanism is released.
19.4.4.3 Aborting conversions
Any conversion in progress is aborted in the following cases:
• A write to ADC_SC1 occurs.
• The current conversion will be aborted and a new conversion will be initiated, if
ADC_SC1[ADCH] are not all 1s and ADC_SC4[AFDEP] are all 0s.
• The current conversion and the rest of conversions will be aborted and no new
conversion will be initialed, if ADC_SC4[AFDEP] are not all 0s.
• A new conversion will be initiated when the FIFO is re-fulfilled upon the levels
indicated by the ADC_SC4[AFDEP] bits).
Chapter 19 Analog-to-digital converter (ADC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 539