Datasheet

Table 3-1. Low power mode behavior (continued)
Mode Run Wait Stop3
RAM On Standby Standby
ADC On On Optional on
ACMP On On Optional on
I/O On On States held
SCI On On Standby
SPI On On Standby
IIC On On Standby
FTM On On Standby
MTIM On On Standby
WDOG On On Optional on
DBG On On Standby
IPC On On Standby
CRC On On Standby
RTC On On Optional on
LVD On On Optional on
3.3 Low voltage detect (LVD) system
This device includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. This
system consists of a power-on reset (POR) circuit and an LVD circuit with a user
selectable trip voltage, either high (V
LVDH
) or low (V
LVDL
). The LVD circuit is enabled
when SPMSC1[LVDE] is set and the trip voltage is selected by SPMSC2[LVDV]. The
LVD is disabled upon entering the stop modes unless the SPMSC1[LVDSE] bit is set or
active BDM enabled (BDCSCR[ENBDM]=1). If SPMSC1[LVDSE] and
SPMSC1[LVDE] are both set, the current consumption in stop3 with the LVD enabled
will be greater.
Low voltage detect (LVD) system
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
54 Freescale Semiconductor, Inc.