Datasheet

the ADC_SC4[AFDEP] bits, no matter whether software or hardware trigger is set. Read
ADC_SC1[ADCH] will read the current active channel value. Write to
ADC_SC1[ADCH] will re-fill channel FIFO to initial new conversion. It will abort
current conversion and any other conversions that did not start. Write to the ADC_SC1
after all the conversions are completed or ADC is in idle state.
The result of the FIFO is accessed by ADC_RH:ADC_RL registers, when FIFO function
is enabled. The result must be read via these two registers by the same order of analog
input channel FIFO to get the proper results. Don't read ADC_RH:ADC_RL until all of
the conversions are completed in FIFO mode. The ADC_SC1[COCO] bit will be set only
when all conversions indicated by the analog input channel FIFO complete whatever
software or hardware trigger is set. An interrupt request will be submitted to CPU if the
ADC_SC1[AIEN] is set when the FIFO conversion completes and the
ADC_SC1[COCO] bit is set.
AD CHANNEL FIFO
AD RESULT FIFO
AFDEP
ADCRL read
ADCRH read
ADCH write
FIFO Read/Write Logic reset
Result FIFO read pointer
Channel FIFO write pointer
Result FIFO write pointer
Channel FIFO read pointer
FIFO conversion start
FIFO Read/Write Logic
FIFO Work Logic
COMPARE
LOGIC
COMPARE
LOGIC
Result FIFO Fulfilled
Channel FIFO Fulfilled
COCO
CK
D
Q
BUS CLK
CK
D
Q
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
16-bit AD result
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
5-bit ch
ADCH
ADCRH
ADCRL
Figure 19-12. FADC FIFO structure
Chapter 19 Analog-to-digital converter (ADC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 543