Datasheet

19.5.2.1 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single
hardware triggered 10-bit 4-level-FIFO conversion at low power with a long sample time
on input channels of 1, 3, 5, and 7. Here the internal ADCK clock is derived from the bus
clock divided by 1.
Example: 19.5.2.1.1 FIFO ADC initialization routine
void ADC_init(void)
{
/* The following code segment demostrates how to initialize ADC by low-power mode, long
sample time, bus frequency, hardwared triggerd from AD1, AD3, AD5, and AD7 external pins
with 4-level FIFO enabled */
ADC_APCTL1 = ADC_APCTL1_ADPC6_MASK | ADC_APCTL1_ADPC5_MASK | ADC_APCTL1_ADPC3_MASK |
ADC_APCTL1_ADPC1_MASK;
ADC_SC3 = ADC_SC3_ADLPC_MASK | ADC_SC3_ADLSMP_MASK | ADC_SC3_MODE1_MASK;
// setting hardware trigger
ADC_SC2 = ADC_SC2_ADTRG_MASK ;
//4-Level FIFO
ADC_SC4 = ADC_SC4_AFDEP1_MASK | ADC_SC4_AFDEP0_MASK;
// dummy the 1st channel
ADC_SC1 = ADC_SC1_ADCH0_MASK;
// dummy the 2nd channel
ADC_SC1 = ADC_SC1_ADCH1_MASK | ADC_SC1_ADCH0_MASK;
// dummy the 3rd channel
ADCSC1 = ADCSC1_ADCH2_MASK | ADC_SC1_ADCH0_MASK;
// dummy the 4th channel and ADC starts conversion
ADC_SC1 = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH2_MASK | ADC_SC1_ADCH1_MASK | ADC_SC1_ADCH0_MASK;
}
Example: 19.5.2.1.2 FIFO ADC interrupt service routine
unsigned short buffer[4];
interrupt VectorNumber_Vadc void ADC_isr(void)
{
/* The following code segment demostrates read AD result FIFO */
// read conversion result of channel 1 and COCO bit is cleared
buffer[0] = ADCR;
// read conversion result of channel 3
buffer[1] = ADCR;
// read conversion result of channel 5
buffer[2] = ADCR;
// read conversion result of channel 7
buffer[3] = ADCR;
}
Chapter 19 Analog-to-digital converter (ADC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 549