Datasheet

Bandgap
+
vD
D
v
ss
v
BG
R
1
R
7
LVDV:LVDWV
LVD0
LVD1
LVD
+
LVW
LVW0
LVW1
LVW2
LVW3
Figure 3-1. Low voltage detect (LVD) block diagram
3.3.1 Power-on reset (POR) operation
When power is initially applied to the MCU, or when the supply voltage drops below the
V
POR
level, the POR circuit will cause a reset condition. As the supply voltage rises, the
LVD circuit will hold the chip in reset until the supply has risen above the V
LVDL
level.
Both the SRS[POR] and SRS[LVD] are set following a POR.
3.3.2 LVD reset operation
The LVD can be configured to generate a reset upon detection of a low voltage condition
by setting SPMSC1[LVDRE] to 1. After an LVD reset has occurred, the LVD system
will hold the MCU in reset until the supply voltage has risen above the level determined
by LVDV. The SRS[LVD] bit is set following either an LVD reset or POR.
3.3.3 Low-voltage warning (LVW)
The LVD system has a low voltage warning flag to indicate that the supply voltage is
approaching the LVD voltage. When a low voltage condition is detected and the LVD
circuit is configured for interrupt operation (SPMSC1[LVDE] set, SPMSC1[LVWIE]
set), SPMSC1[LVWF] will be set and LVW interrupt will occur. There are four user-
selectable trip voltages for the LVW upon each LVDV configuration. The trip voltage is
selected by SPMSC2[LVWV].
Chapter 3 Power management
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 55