Datasheet

+
–
MUX
6-bit
DAC
MUX
Bandgap
DACREF
DACVAL
DACEN
MUX
ACMP0
ACMP1
ACMP2
ACPSEL
ACNSEL
ACE
External Output
Interrupt
ACOPE
Edge Control
Logic
ACMOD ACF ACIEACO
HYST
Note: ACMP2 is reserved for internal test only.
VDDA
Figure 20-1. ACMP block diagram
20.2 External signal description
The output of ACMP can also be mapped to an external pin. When the output is mapped
to an external pin, ACMP_CS[ACOPE] controls the pin to enable/disable the ACMP
output function.
20.3 Memory map and register definition
ACMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
2C ACMP Control and Status Register (ACMP_CS) 8 R/W 00h 20.3.1/560
2D ACMP Control Register 0 (ACMP_C0) 8 R/W 00h 20.3.2/561
2E ACMP Control Register 1 (ACMP_C1) 8 R/W 00h 20.3.3/561
2F ACMP Control Register 2 (ACMP_C2) 8 R/W 00h 20.3.4/562
Chapter 20 Analog comparator (ACMP)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 559