Datasheet

20.3.1 ACMP Control and Status Register (ACMP_CS)
Address: 2Ch base + 0h offset = 2Ch
Bit 7 6 5 4 3 2 1 0
Read
ACE HYST ACF ACIE
ACO
ACOPE ACMOD
Write
Reset
0 0 0 0 0 0 0 0
ACMP_CS field descriptions
Field Description
7
ACE
Analog Comparator Enable
This bit enables the ACMP module.
0 The ACMP is disabled.
1 The ACMP is enabled.
6
HYST
Analoy Comparator Hystersis Selection
This bit is used to select ACMP hystersis.
0 20 mV.
1 30 mV.
5
ACF
ACMP Interrupt Flag Bit
Synchronously set by hardware when ACMP output has a valid edge defined by ACMOD. The setting of
this bit lags the ACMPO 2 bus clocks. Clear ACMPF bit by writing a 0 to this bit. Writing a 1 to this bit has
no effect.
4
ACIE
ACMP Interrupt Enable
Enables an ACMP CPU interrupt.
0 Disable the ACMP Interrupt.
1 Enable the ACMP Interrupt.
3
ACO
ACMP Output
Reading ACO will return the current value of the analog comparator output. ACO is reset to a 0 and will
read as a 0 when the ACMP is disabled (ACE = 0)
2
ACOPE
ACMP Output Pin Enable
ACOPE enables the pad logic so that the output can be placed onto an external pin.
0 ACMP output cannot be placed onto external pin.
1 ACMP output can be placed onto external pin.
1–0
ACMOD
ACMP MOD
Determines the sensitivity modes of the interrupt trigger.
00 ACMP interrupt on output falling edge.
01 ACMP interrupt on output rising edge.
Table continues on the next page...
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
560 Freescale Semiconductor, Inc.