Datasheet

Because the input-switching can cause problems on the ACMP inputs, the user should
complete the input selection before enabling the ACMP and must not change the input
selection setting when the ACMP is enabled to avoid unexpected output. Similarly,
because the DAC experiences a setup delay after the DACVAL is changed, the user
should complete the setting of DACVAL before DAC is enabled.
20.6 Resets
During a reset the ACMP is configured in the default mode. Both CMP and DAC are
disabled.
20.7 Interrupts
If the bus clock is available when a valid edge defined in ACMP_CS[ACMOD] occurs,
the ACMP_CS[ACF] bit register is asserted. If ACMP_CS[ACIE] is set, a ACMP
interrupt event occurs. The ACMP_CS[ACF] bit remains asserted until the ACMP
interrupt is cleared by software. When in stop3 mode, a valid edge on ACMP output
generates an asynchronous interrupt that can wake the MCU from stop3. The interrupt
can be cleared by writing a 0 to the ACMP_CS[ACF] bit.
Resets
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
564 Freescale Semiconductor, Inc.