Datasheet

WAS
CRC_D0
Polynomial
MUX
CRC Engine
NOT
Logic
Reverse
Logic
Reverse
Logic
CRC_D1
CRC_D2
CRC_D3
CRC Data
Seed
Data
Checksum
TOT TOTRFXOR
Combine
Logic
TCRC
CRC_P0
CRC_P1
CRC_P2
CRC_P3
16-/32-bit Select
CRC_D0
CRC_D1
CRC_D2
CRC_D3
Figure 21-1. Cyclic redundancy check (S08CRC) block diagram
21.4 Modes of operation
This section defines the CRC operation in run, wait, and stop modes.
• Run mode - This is the basic mode of operation in which CRC is full functional.
• Wait mode - The CRC module is optional functional
• Stop3 mode - The CRC module is not functional in this low-power standby state.
CRC calculations in progress stop and will resume after the CPU goes into run mode.
21.5 Register definition
CRC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3060 CRC Data 0 Register (CRC_D0) 8 R/W FFh 21.5.1/567
3061 CRC Data 1 Register (CRC_D1) 8 R/W FFh 21.5.2/567
3062 CRC Data 2 Register (CRC_D2) 8 R/W FFh 21.5.3/568
3063 CRC Data 3 Register (CRC_D3) 8 R/W FFh 21.5.4/569
3064 CRC Polynomial 0 Register (CRC_P0) 8 R/W 00h 21.5.5/569
3065 CRC Polynomial 1 Register (CRC_P1) 8 R/W 00h 21.5.6/570
3066 CRC Polynomial 2 Register (CRC_P2) 8 R/W 10h 21.5.7/570
3067 CRC Polynomial 3 Register (CRC_P3) 8 R/W 21h 21.5.8/571
3068 CRC Control Register (CRC_CTRL) 8 R/W 00h 21.5.9/571
Modes of operation
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
566 Freescale Semiconductor, Inc.