Datasheet

21.5.4 CRC Data 3 Register (CRC_D3)
D3 is one of the CRC data registers (D0:D3). The set of CRC data registers contains the
value of seed, data, and checksum. When CRC_CTRL[WAS] bit is set, any write to the
data registers is regarded as seed for CRC module. When CRC_CTRL[WAS] bit is clear,
any write to the data registers is regarded as data for general CRC computation, in which
D0:D2 does not accept any data and D3 accept 8-bit write upon the polynomial
configuration. When final data are written, the final result can be read from the data
register. The registers of D0:D1 contain the MSB 16-bit of CRC data, which is used only
in CRC 32-bit mode. Only D3 is used to dummy data to CRC. Writing D2 will be
ignored when WAS = 0.
Address: 3060h base + 3h offset = 3063h
Bit 7 6 5 4 3 2 1 0
Read
D3
Write
Reset
1 1 1 1 1 1 1 1
CRC_D3 field descriptions
Field Description
7–0
D3
CRC Data Bit 7:0
21.5.5 CRC Polynomial 0 Register (CRC_P0)
P0 is one of the CRC polynomial registers (P0:P3). The set of CRC polynominal registers
contains the value of polynomial. The registers of P0:P1 contain the MSB 16-bit of CRC
polynomial, which is used only in CRC 32-bit mode. The registers of P2:P3 contain the
LSB 16-bit of CRC polynomial, which is used in both CRC 16- and 32-bit modes.
Address: 3060h base + 4h offset = 3064h
Bit 7 6 5 4 3 2 1 0
Read
P0
Write
Reset
0 0 0 0 0 0 0 0
CRC_P0 field descriptions
Field Description
7–0
P0
CRC Polynominal Bit 31:24
Chapter 21 Cyclic redundancy check (CRC)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 569