Datasheet

• Provides robust check that program flow is faster than expected
• Early refresh attempts trigger a reset
• Optional timeout interrupt to allow post-processing diagnostics
• Interrupt request to CPU with interrupt vector for an interrupt service routine
(ISR)
• Forced reset occurs 128 bus clocks after the interrupt vector fetch
• Configuration bits are write-once-after-reset to ensure watchdog configuration cannot
be mistakenly altered
• Robust write sequence for unlocking write-once configuration bits
• Unlock sequence of writing 0xC520 and then 0xD928 within 16 bus clocks for
allowing updates to write-once configuration bits
• Software must make updates within 128 bus clocks after unlocking and before
WDOG closing unlock window.
22.1.2 Block diagram
The following figure provides a block diagram of the WDOG module.
MUX
MUX
MUX
32K CLK
EXT CLK
UPDATE
EN
CLK PRES WIN INT
1K CLK
BUS CLK
256
16-bit Window Register
0xD928
0xC520
Control Status
128 Bus Cycle
Disable Protect
Bit Write Control
Protect
Window
Reset
Counter
Overflow
Counter
Write Control
0xA602
0xB480
16-bit Timeout Value Register
Refresh Sequence
Compare Logic
16-bit Counter Register
Compare Logic
Control
Logic
128 Bus
CPU Reset
IRQ Interrupt
Clock Delay
Backup Reset
Figure 22-1. WDOG block diagram
Introduction
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
576 Freescale Semiconductor, Inc.