Datasheet

22.2 Memory map and register definition
WDOG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3030 Watchdog Control and Status Register 1 (WDOG_CS1) 8 R/W 80h 22.2.1/577
3031 Watchdog Control and Status Register 2 (WDOG_CS2) 8 R/W 01h 22.2.2/579
3032 Watchdog Counter Register: High (WDOG_CNTH) 8 R 00h 22.2.3/580
3033 Watchdog Counter Register: Low (WDOG_CNTL) 8 R 00h 22.2.4/580
3034 Watchdog Timeout Value Register: High (WDOG_TOVALH) 8 R/W 00h 22.2.5/581
3035 Watchdog Timeout Value Register: Low (WDOG_TOVALL) 8 R/W 04h 22.2.6/581
3036 Watchdog Window Register: High (WDOG_WINH) 8 R/W 00h 22.2.7/582
3037 Watchdog Window Register: Low (WDOG_WINL) 8 R/W 00h 22.2.8/582
22.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)
This section describes the function of watchdog control and status register 1.
NOTE
The TST bits are cleared (0:0) on POR only. Any other reset
does not affect the value of these bits.
Address: 3030h base + 0h offset = 3030h
Bit 7 6 5 4 3 2 1 0
Read
EN INT UPDATE TST DBG WAIT STOP
Write
Reset
1 0 0 0 0 0 0 0
WDOG_CS1 field descriptions
Field Description
7
EN
Watchdog Enable
This write-once bit enables the watchdog counter to start counting.
0 Watchdog disabled.
1 Watchdog enabled.
6
INT
Watchdog Interrupt
This write-once bit configures the watchdog to generate an interrupt request upon a reset-triggering event
(timeout or illegal write to the watchdog), prior to forcing a reset. After the interrupt vector fetch, the reset
occurs after a delay of 128 bus clocks.
Table continues on the next page...
Chapter 22 Watchdog (WDOG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 577