Datasheet

WDOG_CS1 field descriptions (continued)
Field Description
0 Watchdog interrupts are disabled. Watchdog resets are not delayed.
1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks.
5
UPDATE
Allow updates
This write-once bit allows software to reconfigure the watchdog without a reset.
0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without
forcing a reset.
1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks
after performing the unlock write sequence.
4–3
TST
Watchdog Test
These bits enable the fast test mode. The test mode allows software to exercise all bits of the counter to
demonstrate that the watchdog is functioning properly. See the "Fast testing of the watchdog" section.
These write-once bits are cleared (0:0) on POR only. Any other reset does not affect the value of these
bits.
00 Watchdog test mode disabled.
01 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software
should use this setting to indicate that the watchdog is functioning normally in user mode.
10 Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with
WDOG_TOVALL.
11 Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with
WDOG_TOVALH.
2
DBG
Debug Enable
This write-once bit enables the watchdog to operate when the chip is in debug mode.
0 Watchdog disabled in chip debug mode.
1 Watchdog enabled in chip debug mode.
1
WAIT
Wait Enable
This write-once bit enables the watchdog to operate when the chip is in wait mode.
0 Watchdog disabled in chip wait mode.
1 Watchdog enabled in chip wait mode.
0
STOP
Stop Enable
This write-once bit enables the watchdog to operate when the chip is in stop mode.
0 Watchdog disabled in chip stop mode.
1 Watchdog enabled in chip stop mode.
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
578 Freescale Semiconductor, Inc.