Datasheet

22.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)
This section describes the function of the watchdog control and status register 2.
Address: 3030h base + 1h offset = 3031h
Bit 7 6 5 4 3 2 1 0
Read
WIN
FLG 0
PRES
0
CLK
Write w1c
Reset
0 0 0 0 0 0 0 1
WDOG_CS2 field descriptions
Field Description
7
WIN
Watchdog Window
This write-once bit enables window mode. See the "Window mode" section.
0 Window mode disabled.
1 Window mode enabled.
6
FLG
Watchdog Interrupt Flag
This bit is an interrupt indicator when INT is set in control and status register 1. Write 1 to clear it.
0 No interrupt occurred.
1 An interrupt occurred.
5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
PRES
Watchdog Prescalar
This write-once bit enables a fixed 256 pre-scaling of watchdog counter reference clock. (The block
diagram shows this clock divider option.)
0 256 prescalar disabled.
1 256 prescalar enabled.
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1–0
CLK
Watchdog Clock
The write-once bits indicate the clock source that feeds the watchdog counter. See the "Clock source"
section.
00 Bus clock.
01 1 kHz internal low-power oscillator (LPOCLK).
10 32 kHz internal oscillator (ICSIRCLK).
11 External clock source.
Chapter 22 Watchdog (WDOG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 579