Datasheet

22.3 Functional description
The WDOG module provides a fail safe mechanism to ensure the system can be reset to a
known state of operation in case of system failure, such as the CPU clock stopping or
there being a run away condition in the software code. The watchdog counter runs
continuously off a selectable clock source and expects to be serviced (refreshed)
periodically. If it is not, it resets the system.
The timeout period, window mode and clock source are all programmable but must be
configured within 128 bus clocks after a reset.
22.3.1 Watchdog refresh mechanism
The watchdog resets the MCU if the watchdog counter is not refreshed. A robust refresh
mechanism makes it very unlikely that the watchdog can be refreshed by runaway code.
To refresh the watchdog counter, software must execute a refresh write sequence before
the timeout period expires. In addition, if window mode is used, software must not start
the refresh sequence until after the time value set in the WDOG_WINH:L registers. See
the following figure.
Chapter 22 Watchdog (WDOG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 583