Datasheet

22.3.4 Using interrupts to delay resets
When interrupts are enabled (WDOG_CS1[INT] = 1), the watchdog first generates an
interrupt request upon a reset triggering event (such as a counter timeout or invalid
refresh attempt). The watchdog delays forcing a reset for 128 bus clocks to allow the
interrupt service routine (ISR) to perform tasks, such as analyzing the stack to debug
code.
When interrupts are disabled (WDOG_CS1[INT] = 0), the watchdog does not delay
forcing a reset.
22.3.5 Backup reset
NOTE
A clock source other than the bus clock must be used as the
reference clock for the counter; otherwise, the backup reset
function is not available.
The backup reset function is a safeguard feature that independently generates a reset in
case the main WDOG logic loses its clock (the bus clock) and can no longer monitor the
counter. If the watchdog counter overflows twice in succession (without an intervening
reset), the backup reset function takes effect and generates a reset.
22.3.6 Functionality in debug and low-power modes
By default, the watchdog is not functional in active background mode, wait mode, or
stop3 mode. However, the watchdog can remain functional in these modes as follows:
• For active background mode, set the WDOG_CS1[DBG] bit. (This way the
watchdog is functional in active background mode even when the CPU is held by the
debug module.)
• For wait mode, set the WDOG_CS1[WAIT] bit.
• For stop3 mode, set the WDOG_CS1[STOP] bit.
NOTE
The watchdog can not generate interrupt in stop3 mode even if
WDOG_CS1[STOP] bit is set and will not wake up MCU from
stop3 mode. It can generate reset during stop3 mode.
Functional description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
588 Freescale Semiconductor, Inc.