Datasheet

For active background mode and stop3 mode, in addition to the
above configurations, a clock source other than the bus clock
must be used as the reference clock for the counter; otherwise,
the watchdog cannot function.
22.3.7 Fast testing of the watchdog
Before executing application code in safety critical applications, users are required to test
that the watchdog works as expected and resets the MCU. Testing every bit of a 16-bit
counter by letting it run to the overflow value takes a relatively long time (64K clocks).
To help minimize the startup delay for application code after reset, the watchdog has a
feature to test the watchdog more quickly by splitting the counter into its constituent
byte-wide stages. The low and high bytes are run independently and tested for timeout
against the corresponding byte of the timeout value register. (For complete coverage
when testing the high byte of the counter, the test feature feeds the input clock via the 8th
bit of the low byte, thus ensuring that the overflow connection from the low byte to the
high byte is tested.)
Using this test feature reduces the test time to 512 clocks (not including overhead, such as
user configuration and reset vector fetches). To further speed testing, use a faster clock
(such as the bus clock) for the counter reference.
On a power-on reset, the POR bit in the system reset register is set, indicating the user
should perform the WDOG fast test.
22.3.7.1 Testing each byte of the counter
The test procedure follows these steps:
1. Program the preferred watchdog timeout value in the WDOG_TOVALH:L registers
during the watchdog configuration time period.
2. Select a byte of the counter to test using the WDOG_CS1[TST] field: 10b for the low
byte; 11b for the high byte.
3. Wait for the watchdog to timeout. Optionally, in the idle loop, increment RAM
locations as a parallel software counter for later comparison. Because the RAM is not
affected by a watchdog reset, the timeout period of the watchdog counter can be
compared with the software counter to verify the timeout period has occurred as
expected.
4. The watchdog counter times out and forces a reset.
5. Confirm the WDOG flag in the system reset register is set, indicating that the
watchdog caused the reset. (The POR flag remains clear.)
Chapter 22 Watchdog (WDOG)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 589