Datasheet

6. Confirm the WDOG_CS1[TST] field shows a test (10b or 11b) was performed.
If confirmed, the count and compare functions work for the selected byte. Repeat the
procedure, selecting the other byte in Step 2.
NOTE
The WDOG_CS1[TST] bits are cleared by a POR reset only
and not affected by other resets.
22.3.7.2 Entering user mode
After successfully testing the low and high bytes of the watchdog counter, the user can
configure WDOG_CS1[TST] to 01b to indicate the watchdog is ready for use in
application user mode. Thus if a reset occurs again, software can recognize the reset
trigger as a real watchdog reset caused by runaway or faulty application code.
As an ongoing test when using the default 1-kHz clock source, software can periodically
read the WDOG_CNTH:L registers to ensure the counter is being incremented.
Functional description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
590 Freescale Semiconductor, Inc.