Datasheet

Section number Title Page
5.2.1.2 Edge and level sensitivity..............................................................................................................125
5.3 Interrupt pin request register...........................................................................................................................................125
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................126
5.4 Interrupt priority control register....................................................................................................................................127
5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................128
5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................129
5.4.3 Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................129
Chapter 6
System control
6.1 System device identification (SDID)..............................................................................................................................131
6.2 Universally unique identification (UUID)......................................................................................................................131
6.3 Reset and system initialization........................................................................................................................................131
6.4 System options................................................................................................................................................................132
6.4.1 BKGD pin enable.............................................................................................................................................132
6.4.2 RESET pin enable............................................................................................................................................132
6.4.3 SCI0 pin reassignment.....................................................................................................................................132
6.4.4 SPI0 pin reassignment......................................................................................................................................132
6.4.5 IIC pins reassignments.....................................................................................................................................133
6.4.6 FTM2 channels pin reassignment....................................................................................................................133
6.4.7 Bus clock output pin enable.............................................................................................................................133
6.5 System interconnection...................................................................................................................................................133
6.5.1 ACMP output selection....................................................................................................................................134
6.5.2 SCI0 TxD modulation......................................................................................................................................134
6.5.3 SCI0 RxD capture............................................................................................................................................135
6.5.4 SCI0 RxD filter................................................................................................................................................135
6.5.5 RTC capture.....................................................................................................................................................136
6.5.6 FTM2 software synchronization......................................................................................................................136
6.5.7 ADC hardware trigger......................................................................................................................................136
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
6 Freescale Semiconductor, Inc.