Datasheet

BDC_SCR field descriptions (continued)
Field Description
0 Target CPU is running user application code or in active background mode (was not in wait or stop
mode when background became active).
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or
stop to active background mode.
1
WSF
Wait or Stop Failure Status
This status bit is set if a memory access command failed due to the target CPU executing a wait or stop
instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command
to get out of wait or stop mode into active background mode, repeat the command that failed, then return
to the user program. (Typically, the host would restore CPU registers and stack values and re-execute the
wait or stop instruction.)
0 Memory access did not conflict with a wait or stop instruction.
1 Memory access command failed because the CPU entered wait or stop mode.
0
DVF
Data Valid Failure Status
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access.
23.4.2 BDC Breakpoint Match Register: High (BDC_BKPTH)
This register, together with BDC_BKPTL, holds the address for the hardware breakpoint
in the BDC. The BKPTEN and FTS control bits in BDCSCR are used to enable and
configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and
WRITE_BKPT) are used to read and write the BDCBKPT register but is not accessible to
user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before
running the user application program.
Address: 0h base + 1h offset = 1h
Bit 7 6 5 4 3 2 1 0
Read
A[15:8]
Write
Reset
0 0 0 0 0 0 0 0
BDC_BKPTH field descriptions
Field Description
7–0
A[15:8]
High 8-bit of hardware breakpoint address.
Chapter 23 Development support
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 607