Datasheet

Table 4-1. Reset and interrupt vectors (continued)
Address
(high/low)
Vector Vector name
0xFFC2:FFC3 SCI2 receive Vsci2rxd
0xFFC4:FFC5 SCI2 error Vsci2err
0xFFC6:FFC7 SCI1 transmit Vsci1txd
0xFFC8:FFC9 SCI1 receive Vsci1rxd
0xFFCA:FFCB SCI1 error Vsci1err
0xFFCC:FFCD SCI0 transmit Vsci0txd
0xFFCE:FFCF SCI0 receive Vsci0rxd
0xFFD0:FFD1 SCI0 error Vsci0err
0xFFD2:FFD3 ADC Vadc
0xFFD4:FFD5 ACMP Vacmp
0xFFD6:FFD7 MTIM1 Vmtim1
0xFFD8:FFD9 MTIM0 Vmtim0
0xFFDA:FFDB FTM0 overflow Vftm0ovf
0xFFDC:FFDD FTM0 channel 1 Vftm0ch1
0xFFDE:FFDF FTM0 channel 0 Vftm0ch0
0xFFE0:FFE1 FTM1 overflow Vftm1ovf
0xFFE2:FFE3 FTM1 channel 1 Vftm1ch1
0xFFE4:FFE5 FTM1 channel 0 Vftm1ch0
0xFFE6:FFE7 FTM2 overflow Vftm2ovf
0xFFE8:FFE9 FTM2 channel 5 Vftm2ch5
0xFFEA:FFEB FTM2 channel 4 Vftm2ch4
0xFFEC:FFED FTM2 channel 3 Vftm2ch3
0xFFEE:FFEF FTM2 channel 2 Vftm2ch2
0xFFF0:FFF1 FTM2 channel 1 Vftm2ch1
0xFFF2:FFF3 FTM2 channel 0 Vftm2ch0
0xFFF4:FFF5 FTM2 fault Vftm2flt
0xFFF6:FFF7 Clock loss of lock Vclk
0xFFF8:FFF9 Low voltage warning Vlvw
0xFFFA:FFFB IRQ or Watchdog Virq or Vwdog
0xFFFC:FFFD SWI Vswi
0xFFFE:FFFF Reset Vreset
4.3 Register addresses and bit assignments
The register definitions vary in different memory sizes. The register addresses of unused
peripherals are reserved. The following table shows the register availability of the
devices.
Chapter 4 Memory map
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 61